Using 2D materials on chips without destroying the wiring

Getting the temperature of TMDs growth down enough to make large-scale manufacturing feasible could be a huge leap toward making 3D stacked CMOS with 2D semiconductors in actual products people can use. Five members of Kim’s team worked at Samsung’s Device Research Center in South Korea, which might make it look like we’re on the verge of getting this technology to market. The problem is that we need at least one more similar leap before we say goodbye to silicon chips.

Doping problem

Currently, we don’t know how to connect TMD semiconductors with other devices. In today’s chips, connections are achieved by doping: injecting the silicon with impurities to increase its conductivity precisely at points where it interfaces with metal wiring. Those injected impurities smooth out the conductivity drop when the signal is moving between semiconductors and highly conductive materials like chromium, copper, or platinum.

At an atomic scale, doping substitutes atoms of a host metal with foreign atoms. But how do you do that when your host material is one atom thin?

There have been attempts to achieve effects somewhat equivalent to doping in 2D molybdenum disulphide, but the process was difficult to control. In Kim’s paper, the team wrote that developing a doping process for TMDs that can be done below 400° Celsius is necessary to build high-performing chips based on 2D semiconductors. The team thinks its technology may help in growing doped TMDs, but so far, we have no way to do so.

Another looming issue is cooling. Getting the heat out of a super densely packed chip is hard enough with a single layer of transistors. Stacking multiple such layers on top of each other should make the issue considerably worse. “A heat sink area is needed in devices like that. This is also something we plan to do in the future—developing a new cooling scheme for such chips,” Kim said.

But Kim argues that these challenges are worth tackling, as he feels 3D stacked chips based on 2D semiconductors will dramatically increase the performance we can get out of the same chip area and significantly lower the power consumption compared to standard CMOS electronics. And all that will be needed for powering future AI systems.

“We will achieve very, very high-density AI chips,” Kim said.

Nature, 2024.  DOI: 10.1038/s41586-024-08236-9